Abstract: The testing and verification technology for system HDL models, focused to the significant improvement of the quality of design components for digital systems on chips and reduction the development time (time-to-market) by using the simulation environment, testable analysis of the logical structure HDL-program and the optimal placement of assertion engine is proposed.
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., & Yves, T. (2010). Assertion based HDL-models testing for SoC components. The International Conference on Electrical Engineering, 7(7th International Conference on Electrical Engineering ICEENG 2010), 1-14. doi: 10.21608/iceeng.2010.33006
MLA
Vladimir Hahanov; Eugenia Litvinova; Wajeb Gharibi; Olesya Guz; Ngene Christopher Umerah; Tiecoura Yves. "Assertion based HDL-models testing for SoC components". The International Conference on Electrical Engineering, 7, 7th International Conference on Electrical Engineering ICEENG 2010, 2010, 1-14. doi: 10.21608/iceeng.2010.33006
HARVARD
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., Yves, T. (2010). 'Assertion based HDL-models testing for SoC components', The International Conference on Electrical Engineering, 7(7th International Conference on Electrical Engineering ICEENG 2010), pp. 1-14. doi: 10.21608/iceeng.2010.33006
VANCOUVER
Hahanov, V., Litvinova, E., Gharibi, W., Guz, O., Umerah, N., Yves, T. Assertion based HDL-models testing for SoC components. The International Conference on Electrical Engineering, 2010; 7(7th International Conference on Electrical Engineering ICEENG 2010): 1-14. doi: 10.21608/iceeng.2010.33006
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