Abstract: This paper presents a real time implementation of Run-Length Decode (RLD) using FPGA as one of image decompression algorithms. The RLD algorithm is the decoder of the Run- Length Encode. RLD can be implemented either on commercial DSP or as an ASIC but due to the huge development in the FPGA field, it is recommended to use the FPGA technology. The design steps from design entry to files which are needed for the download process are developed. Also, the method of testing the downloaded design is explained.
Salama, G., Hassan, F., Bahy, R., & Ibrahim, S. (2006). An Implementation of the Run-Length Decode Algorithm using FPGA. The International Conference on Electrical Engineering, 5(5th International Conference on Electrical Engineering ICEENG 2006), 1-8. doi: 10.21608/iceeng.2006.33505
MLA
Gouda Ismail Salama; Fawzy ELtothamy Hassan; Ramy Mohammed Bahy; Sameh shawky Ibrahim. "An Implementation of the Run-Length Decode Algorithm using FPGA", The International Conference on Electrical Engineering, 5, 5th International Conference on Electrical Engineering ICEENG 2006, 2006, 1-8. doi: 10.21608/iceeng.2006.33505
HARVARD
Salama, G., Hassan, F., Bahy, R., Ibrahim, S. (2006). 'An Implementation of the Run-Length Decode Algorithm using FPGA', The International Conference on Electrical Engineering, 5(5th International Conference on Electrical Engineering ICEENG 2006), pp. 1-8. doi: 10.21608/iceeng.2006.33505
VANCOUVER
Salama, G., Hassan, F., Bahy, R., Ibrahim, S. An Implementation of the Run-Length Decode Algorithm using FPGA. The International Conference on Electrical Engineering, 2006; 5(5th International Conference on Electrical Engineering ICEENG 2006): 1-8. doi: 10.21608/iceeng.2006.33505
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