DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

Rohiem, Alaa El Din; Hassan, Kamel Mohamed; El-Amin, Ahmed M.

doi:10.21608/iceeng.2006.33547

DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

Document Type : Original Article

Authors

Alaa El Din Rohiem
Kamel Mohamed Hassan
Ahmed M. El-Amin

10.21608/iceeng.2006.33547

Abstract

ABSTRACT:
In this paper, we present developed design procedures for a pipelined Advanced
Encryption Standard [AES] encryption algorithm using Field Programmable Gate Array
[FPGA].The design procedures starting from entering the design parameters until
functional simulation and testing have been introduced in this paper. System throughput
of 1.408Gbps has been achieved, whereas the published results for similar systems are
much less than this rate [4-7].

Keywords

FPGA
AES
VHDL
Encryption
decryption

The International Conference on Electrical Engineering

Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006
May 2006
Pages 1-24

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DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006May 2006Pages 1-24

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Volume 5, 5th International Conference on Electrical Engineering ICEENG 2006
May 2006
Pages 1-24