DESIGN OF PIPELINED AES ENCRYPTION ALGORITHM USING FPGA

Document Type : Original Article

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Abstract

ABSTRACT:
In this paper, we present developed design procedures for a pipelined Advanced
Encryption Standard [AES] encryption algorithm using Field Programmable Gate Array
[FPGA].The design procedures starting from entering the design parameters until
functional simulation and testing have been introduced in this paper. System throughput
of 1.408Gbps has been achieved, whereas the published results for similar systems are
much less than this rate [4-7].

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