A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR

Taha, A. K.; Abo El-Soud, M. A.; Abd-EIGhany, F. I.; Mohamed, H. N.

doi:10.21608/iceeng.1998.60209

A NOVEL DESIGN OF AN FPGA-BASED REPROGRAMMABLE DIGITAL CLOCK GENERATOR

Document Type : Original Article

Authors

¹ Ph.D., Head of Dpt. of Electronic Engineering, Military Technical College, Cairo, Egypt.

² Professor, Dpt. of Electronics & Communications, Mansoura University, Mansoura, Egypt.

³ Associate professor, Head of Dpt. of Radar and Guidance,Military Technical Collage, Cairo, Egypt.

⁴ Graduate student, Dpt. of Electronic Engineering, Military Technical Collage, Cairo, Egypt.

10.21608/iceeng.1998.60209

Abstract

This paper presents a novel design of an FPGA-based, reprogrammable digital clock generator that produces a group of clock signals with variable duty cycles. The realized chip provides up to fourty eight, independent, crystal-controlled, variable-duty-cycle clock outputs; each having a duty-cycle that can be varied from 0.4 % to 99.6 % in 250 steps. The proposed design can be used in a variety of applications. One of the main applications is the adjustment of the synaptic weights of an artificial neural network (ANN). The designed unit can also be used as the basis of a highly flexible pulse generator or a complex waveform generator.