Low power, Low Voltage and High Gain UWB Low-Noise Amplifier in the 0.13 μm CMOS technology

Document Type : Original Article

Authors

Faculty of Engineering, Minia University, Minia, Egypt.

Abstract

Abstract:
In this paper, we present a fully integrated CMOS LNA (low noise amplifier) with input
matching LC ladder technique circuitry to cover the upper band of UWB from 3.1 to 10
GHz. Also, an improved technique of derivative superposition (DS) method is proposed
to improve the linearity by using both forward body bias technology, and currentreused.
The proposed LNA can operate at reduced supply voltage and power
consumption. This configuration provides better input matching, lower noise figure, and
more reverse isolation which is vital in LNA design. Complete analytical simulation of
the circuit results in frequency of 3.1 GHz to 10 GHz, with 2.44 dB NFMIN, 50Ω input
impedance, 13.5dB peak power gain (S21), high reverse isolation (S12) -50 dB, -15dB
input matching (S11) and -10dB output matching (S22), while dissipating as low power
as1.5mW low supply voltage of 0.6 V.

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