Abstract: This work presents a hardware implementation of a Genetic Algorithm. Hardware Genetic Operators are implemented in FPGA. Fitness evaluation, which is problem dependent, is left for implementation as S/W module or problem specific hardware design. This allowed a re-configurable general-purpose design, which is customized by application specific population generation and fitness evaluation solution. A 16 site Random Number Generator module is implemented in VHDL based on Hybrid Cellular Automata (CA). Selection, Crossover, and Mutation Operators are implemented as systolic architecture. For preserving locality & modularity of systolic arrays we separate selection array implementation from the crossover and mutation operators. The chromosomes are fed serially to allow variable length chromosomes. The Genetic Engine is targeted a Xilinx Vertex XC2V2000-5 device using Xilinx Foundation Environment. The simulation is carried out using ModelSim.
Mahmoud, I., Salama, M., & Abdel Tawab, A. (2008). Implementation of hardware genetic algorithm. The International Conference on Electrical Engineering, 6(6th International Conference on Electrical Engineering ICEENG 2008), 1-14. doi: 10.21608/iceeng.2008.34332
MLA
Imbaby I. Mahmoud; May Salama; Asmaa Abdel Tawab. "Implementation of hardware genetic algorithm". The International Conference on Electrical Engineering, 6, 6th International Conference on Electrical Engineering ICEENG 2008, 2008, 1-14. doi: 10.21608/iceeng.2008.34332
HARVARD
Mahmoud, I., Salama, M., Abdel Tawab, A. (2008). 'Implementation of hardware genetic algorithm', The International Conference on Electrical Engineering, 6(6th International Conference on Electrical Engineering ICEENG 2008), pp. 1-14. doi: 10.21608/iceeng.2008.34332
VANCOUVER
Mahmoud, I., Salama, M., Abdel Tawab, A. Implementation of hardware genetic algorithm. The International Conference on Electrical Engineering, 2008; 6(6th International Conference on Electrical Engineering ICEENG 2008): 1-14. doi: 10.21608/iceeng.2008.34332
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