FPGA implementation of the BIST intellectual property core for SRAM chips on the board

Document Type : Original Article

Authors

Egyptian Armed Forces.

Abstract

Abstract:
During the last years, much time is spent on the development of Very Large Scale
Integrated (VLSI) Circuits, which are circuits that contain millions of transistors within
a small area. Most ICs are very complex, such that testing is very difficult, and much
work must be done for developing a good test. Memory is considered an important
element in the electronic system. Testing memories on the boards requires a special
testing approach. Testing all these cells for high fault coverage is required. With the
increasing complexity and density of memories, tests must be developed which require
less application time and high fault coverage.
In this paper, an SRAM memory testing architecture using FPGA Spartan-3 System
Board is presented. One of these tests, Modified Algorithmic Test Sequence (MATS),
has been chosen to be implemented in our test architecture. This design is represented as
an IP (Intellectual property) core that is able to perform the BIST (Built-In Self-Test)
for memory on the board. This design is considered as a BIST testing tool for memory
on the complex cards. This approach is considered to reduce the cost of the traditional
ATE that consumes long time. So, our objective is to go step in the direction of the
portable ATE that consumes less time. The hardware implementation occupies less
hardware overhead. The FPGA implementation of this testable architecture
demonstrates the efficiency of the testing approach.

Keywords

Files

Share

How to cite

Statistics