FPGA Implementation of a Direct Digital Synthesizer for Carrier Phase Synchronizer in Software Radio Receiver

Document Type : Original Article

Authors

1 Modern Academy for Engineering and Technology, Cairo, Egypt.

2 College of Engineering, Ain Shams University, Cairo, Egypt.

3 Arab Academy for Engineering and Technology, Cairo, Egypt.

Abstract

Abstract:
More recently there has been a lot of discussion about the emergence of so-called
Software Defined Radio (SDR). Due to its high reconfigurability, Field Programmable
Gate Array technology (FPGA) can be viewed as an attractive option for implementing
many of the tasks performed in SDR. Synchronization is one of the most complicated
signal processing performed in SDR. This paper proposes an all-digital QPSK carrier
phase synchronizer that is based on Phase-Locked Loop. The paper proposes the
implementation of one of the basic block of the synchronizer which is the Numerically
Controlled Oscillator (NCO) based Direct Digital Synthesizer (DDS) on Altera
EPF10K70RC240-4 FPGA chip. A comparison between the simulation results and
Hardware test of the DDS has been made. The used tools are FPGA Advantage Pro
provided by Mentor Graphics and Quartus synthesizer provided by Altera.

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